The present invention relates to a semiconductor memory device which needs a refresh operation, and principally to a technology effective for application to a pseudo static RAM or the like which executes an external read/write operation and a refresh operation executed by an internal circuit during one memory cycle to conceal the refresh operation from outside, thereby being usable equivalently to a static RAM (Random Access Memory) on an equivalent basis.
In order to make it possible to handle a DRAM in a manner similar to an SRAM (Static Random Access Memory), a so-called time multiplex type DRAM wherein a read/write operation and a refresh operation are executed during one cycle with their times being assigned thereto, or the two operations are executed only when the read/write operation and the refresh operation compete with each other, has been proposed in Unexamined Patent Publication No. Sho 61(1985)-71494 (Related Art 1). Further, a pseudo SRAM wherein address transition detectors for a row and a column are respectively provided and a static column operation is controlled based on these detected signals, has been proposed in Unexamined Patent Publication No. Hei 1(1989)-94593 (Related Art 2).